Device isolation techniques play an important role in the design and performance of highly integrated semiconductor circuits by electrically isolating regions and devices therein from adjacent devices and regions. Moreover, as the degree of integration in semiconductor circuits increases, there is a concomitant need to develop techniques for forming isolation regions which are free of defects and can be scaled to provide isolation regions having smaller dimensions, but without sacrificing the isolation capability of the regions.
LOCal Oxidation of Silicon (LOCOS) and Shallow Trench Isolation (STI) are commonly used techniques for forming isolation regions in semiconductor substrates. The LOCOS technique has been widely used because it is relatively simple, however, the LOCOS technique has limitations. In particular, when applied to highly integrated devices such as 256M DRAM devices, oxide thinning and punch-through parasitics may become severe.
To address some of these limitations, STI techniques which include the formation of trench isolation regions have been considered. For example, FIGS. 1A to 1F are cross-sectional views of intermediate structures illustrating a conventional STI technique. In particular, referring to FIG. 1A, a pad oxide film pattern 12 and a silicon nitride film pattern 14 are formed by patterning a pad oxide film and a silicon nitride film to expose a portion of a semiconductor substrate 10 which is to become an isolation region. Then, as shown in FIG. 1B, a trench 16 is formed by etching the semiconductor substrate to a depth of about 3,000 .ANG. to 5,000 .ANG. using the silicon nitride film pattern 14 as an etching mask. Referring now to FIG. 1C, an insulating material layer 20 is formed in the trench 16, and then, as shown in FIG. 1D, a first isolation oxide 22 is formed by etching the insulating material layer 20 until the surface of the silicon nitride film pattern 14 is exposed. After this, as shown in FIG. 1E, the silicon nitride film pattern 14 is removed to define a second isolation oxide 23. Finally, referring to FIG. 1F, the pad oxide film pattern 12 is removed to define a third isolation oxide 24.
The highlighted regions designated as "A" in FIG. 1E and "B" in FIG. 1F show the upper recessed edges of the second and third isolation oxides after removing the silicon nitride film pattern 14 and the pad oxide film pattern 12. As illustrated by region "A", after removing the silicon nitride film pattern 14, the second isolation oxide 23 is in a state in which the edge portion thereof is cut as much as the thickness (t) from the first isolation oxide 22 of FIG. 1D. Also, as illustrated by region B, after removing the pad oxide film pattern 12, the third isolation oxide 24 is in a state in which the edge portion thereof is further cut relative to the second isolation oxide 23 of FIG. 1E. This is because the edge portion of the first isolation oxide 22 is etched to a certain thickness when the silicon nitride film pattern 14 and the pad oxide film pattern 12 are removed. As a result, the upper sidewall portion of the active region (i.e., the upper sidewall portion of the trench 16 which is illustrated as region "C" of FIG. 1F) may be exposed.
Also, there are problems in that the portion of the active region adjacent to the trench 16 is typically formed with a sharp edge. Hereinafter, the problems generated by a sharp edge at the edge of an active region and an exposed upper sidewall of an isolation trench 16 are described. First, a parasitic "hump" phenomenon may occur. The hump phenomenon means that the turn-on characteristics of a transistor formed in the active region may be deteriorated because of the presence of a parasitic transistor (adjacent the sidewall portions of the active region) having a relatively low threshold voltage. Second, an inverse narrow-width effect is generated. The inverse narrow-width effect is also a parasitic phenomenon which lowers the effective threshold voltage as the width of a gate electrode becomes narrower by a strong electric field generated at the sharp edge of the active region. Third, a gate oxide thinning phenomenon is generated whereby the gate oxide film formed at the sharp edge portion of the active region is thinner than the gate oxide film formed in another portion removed from the edge portion. This thinner gate oxide film increases the likelihood of dielectric breakdown which can deteriorate the characteristics of devices formed in the active region.
Thus, notwithstanding the above described methods, there continues to be a need for improved methods of forming field oxide isolation regions.